PCB Process Capability Table
| Item | Mass Production | Sample |
|---|---|---|
| Material | FR4/Ordinary Tg /High Tg /PI/ Low-k/Lead Free/Halogen Free/High Frequency/High Speed | FR4/Ordinary Tg /High Tg /PI/ Low-k/Lead Free/Halogen Free/High Frequency/High Speed/Ceramic/Metal Base/Glass Substrate |
| Type | HDI/Multilayer/FPC/Rigid-Flex/High Frequency/High Speed/Hybrids & Mixed Dielectrics | HDI/Multilayer/FPC/Rigid-Flex/High Frequency/High Speed/Hybrids & Mixed Dielectrics |
| Layer | 2-30 | 2-64 |
| Max HDI Stages | 4+N+4 | Any layer Interconnect |
| PCB Thickness | 0.2-6.0mm | 0.15-20mm |
| Copper Weight | 1/3-6OZ | 1/4-12OZ |
| Mechancial Drill Size（Min） | 6mil（0.15mm） | 5mil（0.127mm） |
| Microvia Hole Size （Min） |
4mil（0.1mm） | 3mil（0.076mm） |
| Trace width/Spacing（Min） | Inner layer2/2mil，Outer layer2.5/2.5mil | Inner layer1.8/1.8mil，Outer layer2/2mil |
| Panel Size （Max） |
800*600mm | 1050*610mm |
| Outline Tolerance （Min） |
±3mil（0.076mm） | 2mil（0.05mm） |
| BGA Pad （Min） |
8mil（0.2mm） | 7mil（0.18mm） |
| Through-Hole Aspect Ratio | 12:1 | 20:1 |
| Blind Via Aspect Ratio | 1:1 | 1:1.2 |
| Impedance Tolerance （Min） |
8%（Single-ended, Differential） | 5%（Single-ended, Differential） |
| Via to Inner Layer Trace Spacing （Min） |
6mil（0.15mm） | 5mil（0.127mm） |
| Level to Level Alignment （Min） |
3mil（0.076mm） | 2mil（0.05mm） |
| Special Process | VIP /Conductive Via Fill /Controlled Depth Drill and Rout/Cavity Boards /Back Drilling/Edge Plating/In‐board Beveling | VIP /Conductive Via Fill /Controlled Depth Drill and Rout/Cavity Boards /Back Drilling/Edge Plating/In‐board Beveling/Buried Capacitance |
| Surface Finishes | ENIG/OSP/HASL/Electric Gold Finger/Electric Hard Gold/Immersion Tin/Immersion Tin/ENIG+OSP/ENEPIG | ENIG/OSP/HASL/Electric Gold Finger/Electric Hard Gold/Immersion Tin/Immersion Tin/ENIG+OSP/ENEPIG |