14-Layer 2-Stage HDI Prototype PCB

14-Layer 2-Stage HDI Prototype PCB Stackup Diagram

The stackup below defines the 14-layer 2-stage HDI build-up. Two build-up sequences on each outer surface deliver the via density needed for BGA 0.2 mm fan-out, while the 10-layer core stack carries the high-speed SerDes, DDR, and power-rail planes. The full table with material, mil/um thicknesses, and tolerances is included in the image below; the explanations that follow are intended to clarify the role of each layer and why the structure is reliable for prototypes that must lead directly into mass production. The same structure is qualified from 5-piece validation lots to volume production, so nothing changes between your prototype release and the mass-production build.

• L1 / L14 (Outer Layers – 1 OZ Copper + Plating): Outer layers are plated to 35 um (1 OZ base) for high-current power delivery and surface-mount land integrity. Outer copper is critical for fine-pitch BGA pads and is paired with ENIG 1-2 u” for long shelf life and coplanarity. Plating uniformity is verified by micro-section on every lot, protecting solder-joint reliability at 0.2 mm BGA pitches.
• L2 / L13 (Sub-Surface Reference and Routing): Sub-surface copper is paired with L1 / L14 references to control impedance for USB 3.0, HDMI 2.1, and high-speed SerDes. These planes also serve as the return path for stage-1 micro-via stubs. Keeping these references unbroken under every stage-1 via transition is what protects eye margins on USB 3.0 and HDMI 2.1 links.
• L3 / L12 (Stage-2 Build-Up Anchor): L3 and L12 anchor the second build-up sequence. Stacked micro-vias from L1->L2->L3 (and L14->L13->L12) enable the 0.2 mm BGA fan-out required by RK3588, RK3568, and equivalent high-pin-count SoCs. Stacked vias share a common land, cutting escape routing length to well under 0.5 mm from the BGA ball to the inner layers.
• L4 / L11 (Power and Slow-Signal Routing): These layers carry SoC core voltage rails, DRAM VTT references, and slower peripherals. Their position next to the central core stack minimises DC-drop for high-current rails. Dedicated VTT and VDDQ islands on these layers keep DDR switching noise out of the analogue supplies.
• L5 / L10 (Core Reference Planes): Adjacent to the central prepreg, L5 and L10 provide solid reference for high-speed SerDes and PCIe Gen 3 lanes routed on L4 / L11. They also balance copper distribution for warp control. Ground vias stitching these planes at approximately 2 mm pitch provide a low-inductance return path across the full 102 x 75 mm panel.
• L6 / L9 (Symmetric Signal Routing): Symmetric routing layers on the inner core, ideal for matched-length DDR and MIPI pairs. The 1.6 mm board thickness with the chosen prepreg stack yields ~100 ohm differential impedance with 4 mil trace geometry. CAM-level pre-route checks hold length-matching tolerances within +/- 5 mil before tooling is released.
• L7 / L8 (Central Power/Ground Sandwich): The central pair is a tightly coupled P/G sandwich that delivers excellent power-rail decoupling for the SoC, DDR, and high-speed PHYs. Plane-to-plane spacing is controlled to ~200 um for low plane inductance. Measured plane impedance stays below 50 mOhm across the 10 MHz to 1 GHz band, protecting the SoC during combined CPU, NPU and DDR load transients.
• FR4 Tg>=170 Base Material: High-Tg FR4 (Tg 170 deg C) is used for all cores and prepregs. The high Tg margin survives multiple lead-free reflow cycles (peak 250 deg C) and long operating life in security and industrial enclosures. Controlled Z-axis expansion protects BGA solder joints for more than 10 years of service in enclosed, fanless installations.
• Build-Up Symmetry and Warp Control: The 2+10+2 structure is symmetric about the central plane, so copper distribution and prepreg balance minimise warp. This matters for fine-pitch BGA assembly and for panel-level prototype yield. Prototype panels are measured for warp and twist below 0.75% at shipment, well inside the IPC limit for fine-pitch BGA assembly.
• Why 2-Stage HDI for RK3588-class Designs: A single-stage HDI board cannot break out a 0.4 mm pitch BGA with 2.5/2.5 mil line/space. The 2-stage build-up with 0.10 mm laser-drilled blind vias on both surfaces is the minimum viable structure for these SoCs. In short: if your design uses a high-pin-count 0.2 mm-pitch SoC, 2-stage HDI is not an optimization option — it is the entry ticket.

This stackup is a proven reference for 14-layer 2-stage HDI prototype boards on FR4 Tg170 material. Our engineering team fine-tunes prepreg selection, copper weights, and via stacking to match the impedance, thickness, and reliability targets of your specific RK3588-class or custom SoC design.